DF2160BVTE10 Renesas Electronics America, DF2160BVTE10 Datasheet - Page 338

IC H8S MCU FLASH 64K 144TQFP

DF2160BVTE10

Manufacturer Part Number
DF2160BVTE10
Description
IC H8S MCU FLASH 64K 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2160BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2160BVTE10
HD64F2160BVTE10
Section 11 16-Bit Free-Running Timer (FRT)
11.7.3
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of
conflict.
If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs
in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of
the automatic addition is not written to OCRA. Figure 11.20 shows the timing for this type of
conflict.
Rev. 3.00 Mar 21, 2006 page 282 of 788
REJ09B0300-0300
Conflict between OCR Write and Compare-Match
Figure 11.19 Conflict between OCR Write and Compare-Match
Address
Internal write
signal
FRC
OCR
Compare-match
signal
(When Automatic Addition Function Is Not Used)
Write cycle of OCR
T 1
OCR address
T 2
N
N
Write data
M
N + 1
Disabled

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