DF2160BVTE10 Renesas Electronics America, DF2160BVTE10 Datasheet - Page 505
![IC H8S MCU FLASH 64K 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2160BVTE10
Manufacturer Part Number
DF2160BVTE10
Description
IC H8S MCU FLASH 64K 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2160BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2160BVTE10
HD64F2160BVTE10
HD64F2160BVTE10
- Current page: 505 of 847
- Download datasheet (5Mb)
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 16.11 shows the sample flowchart for the operations in master receive mode (HNDS = 1).
Figure 16.11 Sample Flowchart for Operations in Master Receive Mode
No
No
Read IRIC flag in ICCR
Set ACKB = 0 in ICSR
Set HNDS = 1 in ICXR
Set ACKB = 1 in ICSR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Set TRS = 0 in ICCR
Master receive mode
Set TRS = 1 in ICCR
Set BBSY = 0 and
SCP = 0 in ICCR
Last receive?
Read ICDR
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
End
Yes
Yes
No
Yes
[1] Select receive mode.
[2] Start receiving. The first read is a dummy read.
[5] Read the receive data (for the second and subsequent read)
[3] Wait for 1 byte to be received.
[4] Clear IRIC flag.
[6] Set acknowledge data for the last reception.
[7] Read the receive data.
[8] Wait for 1 byte to be received.
[9] Clear IRIC flag.
[10] Read the receive data.
[11] Set stop condition issuance.
(HNDS = 1)
(Set IRIC at the rise of the 9th clock for the receive frame)
Dummy read to start receiving if the first frame is
the last receive data.
Generate stop condition.
Section 16 I
Rev. 3.00 Mar 21, 2006 page 449 of 788
2
C Bus Interface (IIC) (Optional)
REJ09B0300-0300
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