DF2160BVTE10 Renesas Electronics America, DF2160BVTE10 Datasheet - Page 582
![IC H8S MCU FLASH 64K 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2160BVTE10
Manufacturer Part Number
DF2160BVTE10
Description
IC H8S MCU FLASH 64K 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2160BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2160BVTE10
HD64F2160BVTE10
HD64F2160BVTE10
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Section 18 Host Interface X-Bus Interface (XBS)
Table 18.9 HIRQ Setting/Clearing Conditions
Host Interrupt
Signal
HIRQ11
(P43)
HIRQ1
(P44)
HIRQ12
(P45)
HIRQ3
(PB0)
HIRQ4
(PB1)
Rev. 3.00 Mar 21, 2006 page 526 of 788
REJ09B0300-0300
No
No
Figure 18.3 HIRQ Output Flowchart (Example of Channels 1 and 2)
Write 1 to P4DR
Write to ODR
Setting Condition
Internal CPU reads 0 from bit P43DR, then
writes 1
Internal CPU reads 0 from bit P44DR, then
writes 1
Internal CPU reads 0 from bit P45DR, then
writes 1
Internal CPU reads 0 from bit PB0ODR,
then writes 1
Internal CPU reads 0 from bit PB1ODR,
then writes 1
P4DR = 0?
transferred?
All bytes
Yes
Yes
Slave CPU
HIRQ output high
HIRQ output low
Clearing Condition
Internal CPU writes 0 in bit P43DR, or
host reads output data register_2
(ODR_2)
Internal CPU writes 0 in bit P44DR, or
host reads output data register_1
(ODR_1)
Internal CPU writes 0 in bit P45DR, or
host reads output data register_1
(ODR_1)
Internal CPU writes 0 in bit PB0ODR,
or host reads output data register_3
(ODR_3)
Internal CPU writes 0 in bit PB1ODR,
or host reads output data register_4
(ODR_4)
Hardware operations
Software operations
Interrupt initiation
Master CPU
ODR read
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