MC9S12XDP512CAG Freescale Semiconductor, MC9S12XDP512CAG Datasheet - Page 419

IC MCU 512K FLASH 144-LQFP

MC9S12XDP512CAG

Manufacturer Part Number
MC9S12XDP512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDP512CAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (24-ch x 10-bit)
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
119
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
For Use With
DEMO9S12XDT512E - BOARD DEMO FOR MC9S12XDT512EVB9S12XDP512E - BOARD DEMO FOR MC9S12XDP512
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 10
Freescale’s Scalable Controller Area Network
(S12MSCANV3)
10.1
Introduction
Freescale’s scalable controller area network (S12MSCANV3) definition is based on the MSCAN12
definition, which is the specific implementation of the MSCAN concept targeted for the M68HC12
microcontroller family.
The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the
Bosch specification dated September 1991. For users to fully understand the MSCAN specification, it is
recommended that the Bosch specification be read first to familiarize the reader with the terms and
concepts contained within this document.
Though not exclusively intended for automotive applications, CAN protocol is designed to meet the
specific requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI
environment of a vehicle, cost-effectiveness, and required bandwidth.
MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified
application software.
10.1.1
Glossary
ACK: Acknowledge of CAN message
CAN: Controller Area Network
CRC: Cyclic Redundancy Code
EOF: End of Frame
FIFO: First-In-First-Out Memory
IFS: Inter-Frame Sequence
SOF: Start of Frame
CPU bus: CPU related read/write data bus
CAN bus: CAN protocol related serial bus
oscillator clock: Direct clock from external oscillator
bus clock: CPU bus realated clock
CAN clock: CAN protocol related clock
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
419

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