MC9S12XDP512CAG Freescale Semiconductor, MC9S12XDP512CAG Datasheet - Page 700
MC9S12XDP512CAG
Manufacturer Part Number
MC9S12XDP512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of MC9S12XDP512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (24-ch x 10-bit)
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
119
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
For Use With
DEMO9S12XDT512E - BOARD DEMO FOR MC9S12XDT512EVB9S12XDP512E - BOARD DEMO FOR MC9S12XDP512
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XDP512CAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDP512CAG
Manufacturer:
FREESCLA
Quantity:
20 000
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Chapter 19 S12X Debug (S12XDBGV2) Module
19.3.1.4
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
702
CDCM[3:2]
ABCM[1:0]
0x0023
Reset
Field
3–2
1–0
W
R
C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
described in
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in
Debug Control Register2 (DBGC2)
0
0
7
TRANGE
TALIGN
Unimplemented or Reserved
11
00
01
10
11
Table
Table
0
0
6
19-14.
19-15.
Table 19-11. TRCMOD Trace Mode Bit Encoding
Table 19-12. TALIGN Trace Alignment Encoding
Figure 19-6. Debug Control Register2 (DBGC2)
TRCMOD
Table 19-10. TRANGE Trace Range Encoding
00
01
10
11
Table 19-13. DBGC2 Field Descriptions
Trace only in range from comparator C to comparator D
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
Trace buffer entries before and after trigger
Trigger at end of stored data
Trigger before storing data
0
0
4
Tracing Source
Description
Description
Reserved
0
3
Description
NORMAL
Reserved
DETAIL
LOOP1
CDCM
0
2
Freescale Semiconductor
0
1
ABCM
0
0
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