D12312SVF20V Renesas Electronics America, D12312SVF20V Datasheet - Page 397

• Manufacturer Part Number: D12312SVF20V
• Description: IC H8S/2312S MCU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVF20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.4.7
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 9.8 shows the correspondence between external clock pins and channels.
Table 9.8
Channels
When channel 1 or 5 is set to phase counting mode
When channel 2 or 4 is set to phase counting mode
Example of Phase Counting Mode Setting Procedure: Figure 9.28 shows an example of the
phase counting mode setting procedure.
Select phase counting mode
<Phase counting mode>
Phase Counting Mode
Phase counting mode
Phase Counting Mode Clock Input Pins
Figure 9.28 Example of Phase Counting Mode Setting Procedure
Start count
[1]
[2]
[1] Select phase counting mode with bits MD3 to
[2] Set the CST bit in TSTR to 1 to start the count
MD0 in TMDR.
operation.
Rev.7.00 Feb. 14, 2007 page 363 of 1108
A-Phase
TCLKA
TCLKC
Section 9 16-Bit Timer Pulse Unit (TPU)
External Clock Pins
B-Phase
TCLKB
TCLKD
REJ09B0089-0700