M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 78

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
Outline Performance
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten.
In CPU rewrite mode, the CPU erases, programs and reads the
internal flash memory as instructed by software commands. This
rewrite control program must be transferred to internal RAM
area before it can be executed.
The MCU enters CPU rewrite mode by setting “1” to the CPU
rewrite mode select bit (bit 1 of address 0FE0
commands can be accepted.
Use software commands to control program and erase
operations. Whether a program or erase operation has terminated
normally or in error can be verified by reading the status register.
Figure 71 shows the flash memory control register 0.
Bit 0 of the flash memory control register 0 is the RY/BY status
flag used exclusively to read the operating status of the flash
memory. During programming and erase operations, it is “0”
(busy). Otherwise, it is “1” (ready).
Bit 1 of the flash memory control register 0 is the CPU rewrite
mode select bit. When this bit is set to “1”, the MCU enters CPU
rewrite mode. And then, software commands can be accepted. In
CPU rewrite mode, the CPU becomes unable to access the
internal flash memory directly. Therefore, use the control
program in the internal RAM for write to bit 1. To set this bit 1 to
“1”, it is necessary to write “0” and then write “1” in succession
to bit 1. The bit can be set to “0” by only writing “0”.
Bit 2 of the flash memory control register 0 is the user block 1
E/W enable bit. By setting combination of bit 4 (user block 0
E/W enable bit) of the flash memory control register 2 (address
0FE2
user block in the CPU rewriting mode.
Bit 3 of the flash memory control register 0 is the flash memory
reset bit used to reset the control circuit of internal flash memory.
This bit is used when flash memory access has failed. When the
CPU rewrite mode select bit is “1”, setting “1” for this bit resets
the control circuit. To release the reset, it is necessary to set this
bit to “0”.
Bit 5 of the flash memory control register 0 is the User ROM
area select bit and is valid only in the boot mode. Setting this bit
to “1” in the boot mode switches an accessible area from the boot
ROM area to the user ROM area. To use the CPU rewrite mode
in the boot mode, set this bit to “1”. To rewrite bit 5, execute the
user original reprogramming control software transferred to the
internal RAM in advance.
Bit 6 of the flash memory control register 0 is the program status
flag. This bit is set to “1” when writing to flash memory is failed.
When program error occurs, the block cannot be used.
Bit 7 of the flash memory control register 0 is the erase status
flag.
This bit is set to “1” when erasing flash memory is failed. When
erase error occurs, the block cannot be used.
Figure 72 shows the flash memory control register 1.
Bit 0 of the flash memory control register 1 is the Erase suspend
enable bit. By setting this bit to “1”, the erase suspend mode to
suspend erase processing temporary when block erase command
is executed can be used. In order to set this bit 0 to “1”, writing
“0” and “1” in succession to bit 0. In order to set this bit to “0”,
write “0” only to bit 0.
Bit 1 of the flash memory control register 1 is the erase suspend
request bit. By setting this bit to “1” when erase suspend enable
bit is “1”, the erase processing is suspended.
Bit 6 of the flash memory control register 1 is the erase suspend
flag. This bit is cleared to “0” at the flash erasing.
16
) and this bit as shown in Table 17, E/W is disabled to
May 20, 2008 Page 76 of 134
16
). Then, software
Fig 71. Structure of flash memory control register 0
Fig 72. Structure of flash memory control register 1
b7
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
b7
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
2: This bit can be written only when CPU rewrite mode select bit is “1”.
3: Effective only when the CPU rewrite mode select bit = “1”. Fix this
4: When setting this bit to “1” (when the control circuit of flash memory
5: Write to this bit in program on RAM
2: Effective only when the suspend enable bit = “1”.
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
is reset), the flash memory cannot be accessed for 10 ms.
bit to “0” when the CPU rewrite mode select bit is “0”.
b0
b0
Flash memory control register 0
(FMCR0: address : 0FE0
RY/BY status flag
0 : Busy (being written or erased)
1 : Ready
CPU rewrite mode select bit
0 : CPU rewrite mode invalid
1 : CPU rewrite mode valid
User block 1 E/W enable bit
0 : E/W disabled (1800
1 : E/W enabled (1800
Flash memory reset bit
0 : Normal operation
1 : reset
Not used (do not write “1” to this bit.)
User ROM area select bit
0 : Boot ROM area is accessed
1 : User ROM area is accessed
Program status flag
0: Pass
1: Error
Erase status flag
0: Pass
1: Error
Flash memory control register 1
(FMCR1: address: 0FE1
Erase Suspend enable bit
0 : Suspend invalid
1 : Suspend valid
Erase Suspend request bit
0 : Erase restart
1 : Suspend request
Not used (do not write “1” to this bit.)
Erase Suspend flag
0 : Erase active
1 : Erase inactive (Erase Suspend mode)
Not used (do not write “1” to this bit.)
16
16
(3, 4)
-7FFF
-7FFF
16
16
(5)
, initial value: 01
(1)
, initial value: 40
(2)
(1, 2)
(1)
16
16
)
)
16
16
)
)