M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 31

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
Fig. 18 Interrupt control
• Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor
status register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is
set to “0”, acceptance of interrupt requests is enabled. This flag is
set to “1” with the SEI instruction and set to “0” with the CLI
instruction.
When an interrupt request is accepted, the contents of the
processor status register are pushed onto the stack while the
interrupt disable flag remains set to “0”. Subsequently, this flag
is automatically set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
• Interrupt Request Bits
Once an interrupt request is generated, the corresponding
interrupt request bit is set to “1” and remains “1” until the request
is accepted . Wh en the request is accepted, th is bit is
automatically set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
• Interrupt Enable Bits
The interrupt enable bits control the acceptance of the
corresponding interrupt requests. When an interrupt enable bit is
set to “0”, the acceptance of the corresponding interrupt request
is disabled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Interrupt request bit
Interrupt enable bit
May 20, 2008 Page 29 of 134
Interrupt disable flag (I)
BRK instruction
Reset
• Interrupt Source Selection
Any of the following combinations can be selected by the
interrupt edge selection register (003A
• External Interrupt Pin Selection
For external interrupts INT
switch bit in the interrupt edge selection register (bits 4 and 5 of
address 003A
or INT
• Timer Y or CNTR
10
and INT
16
) can be used to select INT
11
pin input.
1
0
and INT
1
Interrupt
acceptance
, the INT
16
).
00
and INT
0
, INT
01
1
input port
pin input