M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 41

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
• Frequency Divider For Timer
Each timer X and timer Y have the frequency dividers for the
count source. The count source of the frequency divider is
switched to X
4 in the on-chip oscillator mode by the CPU mode register. The
division ratio of each timer can be controlled by each timer
division ratio selection bit. The division ratio can be selected
from as follows;
1/1, 1/2, 1/16, 1/256 of f(X
Switch the frequency division or count source* while the timer
count is stopped.
*This also applies when the frequency divider output is selected
• Timer X
The count source for timer X can be set using the timer X mode
register. X
selected, count operation is possible regardless of whether or not
the X
The timer X operates as down-count. When the timer contents
reach “0000
the timer latch contents are reloaded. After that, the timer
continues countdown. When the timer underflows, the interrupt
request bit corresponding to the timer X is set to “1”.
Six operating modes can be selected for timer X by the timer X
mode register and timer X control register.
(1) Timer Mode
The count source can be selected by setting the timer X mode
register. In this mode, timer X operates as the 18-bit counter by
setting the timer X register (extension).
(2) Pulse Output Mode
Pulses of which polarity is inverted each time the timer
underflows are output from the T
mode operates just as in the timer mode.
When using this mode, set the port sharing the T
output mode.
(3) IGBT Output Mode
After dummy output from the T
INT
active edge switch bit is “0”, when the trigger is detected or the
timer X underflows, “H” is output from the T
then, when the count value corresponds with the compare
register 1 value, the T
After noise is cleared by noise filters, judging continuous 4-time
same levels with sampling clocks to be signals, the INT
can use 4 types of delay time by a delay circuit.
When using this mode, set the port sharing the INT
mode and set the port sharing the pin used as T
function to output mode.
When the timer X output control bit 1 or 2 of the timer X control
register is set to “1”, the timer X count stop bit is fixed to “1”
forcibly by the interrupt signal of INT
T
the same time that the timer X stops counting.
Do not write “1” to the timer X register (extension) when using
the IGBT output mode.
XOUT1
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (on-
chip oscillator mode, X
careful when changing settings in the CPU mode register.
0
IN
pin input as a trigger. In the case that the timer X output 1
input oscillator or the on-chip oscillator is operating.
output and T
CIN
16
IN
”, an underflow occurs at the next count pulse and
May 20, 2008 Page 39 of 134
may be selected as the count source. If X
, X
CIN
XOUT1
XOUT2
, or the on-chip oscillator OCO divided by
IN
IN
output becomes “L”.
output can be set to “L” forcibly at
), f(X
mode, or low-speed mode). Be
XOUT1
XOUT1
CIN
) or f(OCO)/4.
pin, count starts with the
1
pin. Except for that, this
or INT
XOUT1
XOUT1
2
. And then, the
0
XOUT1
pin to input
or T
pin. And
0
XOUT2
CIN
pin to
signal
is
(4) PWM Mode
IGBT dummy output, an external trigger with the INT
output control with pins INT
those, this mode operates just as in the IGBT output mode.
The period of PWM waveform is specified by the timer X set
value. In the case that the timer X output 1 active edge switch bit
is “0”, the “H” interval is specified by the compare register 1 set
value. In the case that the timer X output 2 active edge switch bit
is “0”, the “H” interval is specified by the compare registers 2
and 3 set values.
When using this mode, set the port sharing the pin used as
T
Do not write “1” to the timer X register (extension) when using
the PWM mode.
(5) Event Counter Mode
The timer counts signals input through the CNTR
mode, timer X operates as the 18-bit counter by setting the timer
X register (extension). When using this mode, set the port
sharing the CNTR
In this mode, the window control can be performed by the timer
1 underflow. When the bit 5 (data for control of event counter
window) of the timer X mode register is set to “1”, counting is
stopped at the next timer 1 underflow. When the bit is set to “0”,
counting is restarted at the next timer 1 underflow.
(6) Pulse Width Measurement Mode
In this mode, the count source is the output of frequency divider
for timer. In this mode, timer X operates as the 18-bit counter by
setting the timer X register (extension). When the bit 6 of the
CNTR
during the “H” interval of CNTR
counting is executed during the “L” interval of CNTR
When using this mode, set the port sharing the CNTR
input mode.
Also, set to enable (“0”) the data for control of event counter
window (bit 5 of timer X mode register (address 002D
XOUT1
0
or T
active edge switch bits is “0”, counting is executed
XOUT2
0
function to output mode.
pin to input mode.
1
and INT
0
pin input. When the bit is “1”,
2
are not used. Except for
0
pin. In this
0
16
pin input.
0
)).
0
pin and
pin to