M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 45

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
<Notes on Timer Y>
• CNTR
CNTR
switch bit. However, in pulse width HL continuously
measurement mode, CNTR
both rising and falling edges of CNTR
regardless of the setting of CNTR
• Timer Y Read/Write Control
• When reading from/writing to timer Y, read from/write to both
• Which write control can be selected by the timer Y write
Fig. 32 Structure of Timer Y related registers
the high-order and low-order bytes of timer Y. When the value
is read, read the high-order bytes first and the low-order bytes
next. When the value is written, write the low-order bytes first
and the high-order bytes next.
Write to or read from the timer Y register by the 16-bit unit. If
reading from the timer Y register during write operation or
writing to it during read operation is performed, normal
operation will not be performed.
control bit (b0) of the timer Y control register (address
0039
same time or writing data only to the latch. When writing a
value to the timer Y address to write to the latch only, the
value is set into the reload latch and the timer is updated at the
next underflow. After reset release, when writing a value to the
timer Y address, the value is set into the timer and the timer
latch at the same time, because they are set to write at the same
time.
When writing to the latch only, if the write timing to the high-
order reload latch and the underflow timing are almost the
same, the value is set into the timer and the timer latch at the
same time. In this time, counting is stopped during writing to
the high-order reload latch.
b7
1
16
interrupt active edge depends on the CNTR
1
), writing data to both the latch and the timer at the
Interrupt Active Edge Selection
May 20, 2008 Page 43 of 134
b0
1
Timer Y mode register
(TYM: address 0038
Real time port 1 control bit (P5
Real time port 2 control bit (P5
RTP
RTP
Timer Y operating mode bits
CNTR
Timer Y count stop bit
interrupt request is generated at
0 : Real time port function invalid
1 : Real time port function valid
0 : Real time port function invalid
1 : Real time port function valid
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuous measurement mode
0 : Count at rising edge in event counter mode
1 : Count at falling edge in event counter mode
0 : Count operation
1 : Count stop
Measure rising period in period measurement mode
0
1
Measure falling period in period measurement mode
Falling edge active for CNTR
Rising edge active for CNTR
1
data for real time port
data for real time port
1
active edge switch bit.
active edge switch bit
16
1
)
pin input signal
1
0
1
)
)
active edge
1
1
interrupt
interrupt
• Switch the frequency division or count source* while the timer
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (on-chip
oscillator mode, XIN mode, or low-speed mode). Be careful
when changing settings in the CPU mode register.
count is stopped.
b7
Note1: φSOURCE indicates the followings:
•X
•Internal on-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
IN
input in the frequency/2, 4, or 8 mode
b0
Timer Y control register
(TYCON: address 0039
Timer Y write control bit
Timer Y count source selection bit
Timer Y frequency division selection bits
Not used (returns “0” when read)
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
0 : Frequency divider output
1 : f(X
b3 b2
0 0 : 1/16 × φSOURCE
0 1 : 1/1 × φSOURCE
1 0 : 1/2 × φSOURCE
1 1 : 1/256 × φSOURCE
CIN
)
16
(1)
)