MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 667

• Manufacturer Part Number: MC9S12XET256CAG
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.0.3
Read: Anytime
Write: Anytime
17.3.0.4
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0002
Module Base + 0x0003
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
PFLT[7:0]
PCE[7:0]
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
7:0
7:0
W
W
R
R
PMUX7
PCE7
PIT Force Load Bits for Timer 7-0 — These bits have only an effect if the corresponding timer channel (PCE
set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding
16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will
always return zero.
PIT Enable Bits for Timer Channel 7:0 — These bits enable the PIT channels 7-0. If PCE is cleared, the PIT
channel is disabled and the corresponding flag bit in the PITTF register is cleared. When PCE is set, and if the
PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-
counting.
0 The corresponding PIT channel is disabled.
1 The corresponding PIT channel is enabled.
PIT Channel Enable Register (PITCE)
PIT Multiplex Register (PITMUX)
0
0
7
7
PMUX6
PCE6
0
0
6
6
Figure 17-5. PIT Channel Enable Register (PITCE)
Figure 17-6. PIT Multiplex Register (PITMUX)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 17-3. PITFLT Field Descriptions
Table 17-4. PITCE Field Descriptions
PMUX5
PCE5
5
0
5
0
PMUX4
PCE4
0
0
4
4
Description
Description
PMUX3
PCE3
0
0
3
3
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
PMUX2
PCE2
2
0
2
0
PMUX1
PCE1
0
0
1
1
PMUX0
PCE0
0
0
0
0
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