MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 145

• Manufacturer Part Number: MC9S12XET256CAG
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
2.3.50
2.3.51
Freescale Semiconductor
Address 0x025D
Address 0x025E
Write: Anytime.
Write: Anytime.
Read: Anytime.
PPSP
Field
Field
PIEP
Reset
Reset
7-0
7-0
W
W
R
R
Port P pull device select—Determine pull device polarity on input pins
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-
up or pull-down device if enabled.
1 A rising edge on the associated Port P pin sets the associated flag bit in the PIFP register. A pull-down device is
0 A falling edge on the associated Port P pin sets the associated flag bit in the PIFP register.A pull-up device is
Port P interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
PPSP7
PIEP7
Port P Polarity Select Register (PPSP)
Port P Interrupt Enable Register (PIEP)
connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
0
0
7
7
PPSP6
PIEP6
0
0
6
6
Figure 2-49. Port P Interrupt Enable Register (PIEP)
Figure 2-48. Port P Polarity Select Register (PPSP)
Table 2-46. PPSP Register Field Descriptions
Table 2-47. PPSP Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
PPSP5
PIEP5
0
0
5
5
PPSP4
PIEP4
0
0
4
4
Description
Description
PPSP3
PIEP3
3
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PPSP2
PIEP2
0
0
2
2
Access: User read/write
Access: User read/write
PPSP1
PIEP1
0
0
1
1
PPSP0
PIEP0
0
0
0
0
145
(1)
(1)