MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 237

• Manufacturer Part Number: MC9S12XET256CAG
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.1.4
Read: Anytime
Write: Never
4.3.1.5
Read: Anytime
Write: Anytime
Freescale Semiconductor
Address: Module Base + 0x0003
Address: Module Base + 0x0005
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
ADDR[7:0]
SEL[2:0]
Reset
Reset
SVSEN
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
7–0
2–0
7
W
W
R
R
SVSEN
MPU Address Status Register 2 (MPUASTAT2)
MPU Descriptor Select Register (MPUSEL)
Access violation address bits — The ADDR[7:0] bits contain bits [7:0] of the global address which caused
the current access violation interrupt. These bits are undefined if the access error flag bit (AEF) in the MPUFLG
register is not set.
MPU supervisor state enable bit — This bit enables the memory protection for the CPU in supervisor state.
If this bit is cleared, the MPU does not affect any accesses coming from the CPU in supervisor state. This is to
prevent the CPU from locking out itself while configuring the protection descriptors (during initialization after a
system reset and during the update of the protection descriptors for a task switch). The memory protection
functionality for the other bus-masters is unaffected by this bit.
0 MPU is disabled for the CPU in supervisor state
1 MPU is enabled for the CPU in supervisor state
Descriptor select bits — The SEL[2:0] bits select which descriptor is visible in the MPU Descriptor Register
window (MPUDESC0—MPUDESC5).
0
0
7
7
Figure 4-6. MPU Address Status Register (MPUASTAT2)
0
0
0
Figure 4-7. MPU Descriptor Select Register (MPUSEL)
6
6
MC9S12XE-Family Reference Manual Rev. 1.23
Table 4-6. MPUASTAT2 Field Descriptions
Table 4-7. MPUSEL Field Descriptions
5
0
5
0
0
0
0
0
4
4
ADDR[7:0]
Description
Description
0
0
0
3
3
Chapter 4 Memory Protection Unit (S12XMPUV1)
2
0
2
0
SEL[2:0]
0
0
1
1
0
0
0
0
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