MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 356

• Manufacturer Part Number: MC9S12XET256CAG
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)
XGATE Channel ID
XGATE Priority Level
XGATE Register Bank
XGATE Channel Interrupt
XGATE Software Channel
XGATE Semaphore
XGATE Thread
XGATE Debug Mode
XGATE Software Error
Word
Byte
10.1.2
The XGATE module includes these features:
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A 7-bit identifier associated with an XGATE channel. In S12XE designs valid Channel IDs range
from $0D to $78.
A priority ranging from 1 to 7 which is associated with an XGATE channel. The priority level of
an XGATE channel is selected in the S12X_INT module.
A register bank consists of registers R1-R7, CCR and the PC. Each interrupt level is associated with
one register bank.
An S12X_CPU interrupt that is triggered by a code sequence running on the XGATE module.
Special XGATE channel that is not associated with any peripheral service request. A Software
Channel is triggered by its Software Trigger Bit which is implemented in the XGATE module.
A set of hardware flip-flops that can be exclusively set by either the S12X_CPU or the XGATE.
(see
A code sequence which is executed by the XGATE’s RISC core after receiving an XGATE request.
A special mode in which the XGATE’s RISC core is halted for debug purposes. This mode enables
the XGATE’s debug features (see
The XGATE is able to detect a number of error conditions caused by erratic software (see
Section 10.4.5, “Software Error
program execution and flag an Interrupt to the S12X_CPU.
A 16 bit entity.
An 8 bit entity.
Data movement between various targets (i.e. Flash, RAM, and peripheral modules)
Data manipulation through built in RISC core
Features
Section 10.4.4,
“Semaphores”)
MC9S12XE-Family Reference Manual , Rev. 1.23
Detection”). These error conditions will cause the XGATE to seize
Section 10.6, “Debug
Mode”).
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