MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 618

no-image

MC9S12XET256CAG

Manufacturer Part Number
MC9S12XET256CAG
Description
MCU 16BIT 256K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XET256CAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XE
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XET256CAG
Manufacturer:
FREESCALE
Quantity:
1 701
Part Number:
MC9S12XET256CAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XET256CAG
Manufacturer:
FREESCALE
Quantity:
1 701
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
16.3.2.4
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
1. Read: Anytime
1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).
618
Module Base + 0x0003
TSEG2[2:0]
TSEG1[3:0]
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
SAMP
Field
6-4
3-0
7
Reset:
W
R
Sampling — This bit determines the number of CAN bus samples taken per bit time.
0 One sample per bit.
1 Three samples per bit
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
Table
Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
Table
MSCAN Bus Timing Register 1 (CANBTR1)
SAMP
0
7
16-9.
16-10.
BRP5
0
0
0
0
1
:
Figure 16-7. MSCAN Bus Timing Register 1 (CANBTR1)
TSEG22
BRP4
0
0
0
0
1
Table 16-8. CANBTR1 Register Field Descriptions
:
6
0
MC9S12XE-Family Reference Manual , Rev. 1.23
(1)
Figure
Figure
BRP3
.
0
0
0
0
1
:
Table 16-7. Baud Rate Prescaler
TSEG21
16-44). Time segment 2 (TSEG2) values are programmable as shown in
16-44). Time segment 1 (TSEG1) values are programmable as shown in
0
5
BRP2
0
0
0
0
1
:
TSEG20
BRP1
4
0
0
0
1
1
1
:
Description
BRP0
TSEG13
0
1
0
1
1
:
0
3
TSEG12
Prescaler value (P)
2
0
64
1
2
3
4
:
Access: User read/write
TSEG11
Freescale Semiconductor
0
1
TSEG10
0
0
(1)

Related parts for MC9S12XET256CAG