S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 518
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Electrical Characteristics
A.3
A.3.1
The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV
register. The frequency of this derived clock must be set within the limits specified as f
module does not have any means to monitor the frequency and will not prevent program or erase operation
at frequencies above or below the specified minimum. When attempting to program or erase the NVM
module at a lower frequency, a full program or erase transition is not assured.
The following sections provide equations which can be used to determine the time required to execute
specific flash commands. All timing parameters are a function of the bus clock frequency, f
program and erase times are also a function of the NVM operating frequency, f
timing parameters can be found in
A.3.1.1
The time required to perform a blank check on all blocks is dependent on the location of the first non-blank
word starting at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the
command. Assuming that no non-blank location is found, then the time to erase verify all blocks is given
by:
A.3.1.2
The time required to perform a blank check is dependent on the location of the first non-blank word starting
at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command.
Assuming that no non-blank location is found, then the time to erase verify a P-Flash block is given by:
Assuming that no non-blank location is found, then the time to erase verify a D-Flash block is given by:
518
t
t
t
check
dcheck
pcheck
NVM
=
=
=
Timing Parameters
35500
2800
Erase Verify All Blocks (Blank Check) (FCMD=0x01)
Erase Verify Block (Blank Check) (FCMD=0x02)
33500
⋅
⋅
⋅
-------------------- -
f
-------------------- -
f
NVMBUS
NVMBUS
-------------------- -
f
NVMBUS
1
1
1
S12P-Family Reference Manual, Rev. 1.13
Table
A-18.
NVMOP
Freescale Semiconductor
. A summary of key
NVMOP
NVMBUS
. The NVM
. All
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