S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 161
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Read: Anytime
Write: Never
6.3.2.3
Read: Anytime
Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed.
Freescale Semiconductor
Address: 0x0022
TSOURCE
SSF[2:0]
Reset
Field
Field
TBF
2–0
7
6
W
R
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF
bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization.
Other system generated resets have no affect on this bit
This bit is also visible at DBGCNT[7]
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal event, then the state sequencer returns to state0
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See
Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU
system is secured, this bit cannot be set and tracing is inhibited.
This bit must be set to read the trace buffer.
0 Debug session without tracing requested
1 Debug session with tracing requested
Debug Trace Control Register (DBGTCR)
0
0
7
TSOURCE
Table 6-6. SSF[2:0] — State Sequence Flag Bit Encoding
0
6
Figure 6-5. Debug Trace Control Register (DBGTCR)
101,110,111
SSF[2:0]
000
001
010
011
100
Table 6-7. DBGTCR Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
Table 6-5. DBGSR Field Descriptions
0
0
5
0
0
4
Description
Description
State0 (disarmed)
Current State
Final State
Reserved
0
State1
State2
State3
3
TRCMOD
Table 6-6
0
2
S12S Debug Module (S12SDBGV2)
.
0
0
1
TALIGN
0
0
161
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