S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 308
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Analog-to-Digital Converter (ADC12B10C)
9.2
This section lists all inputs to the ADC12B10C block.
9.2.1
9.2.1.1
This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger
for the ATD conversion.
9.2.1.2
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connection of these inputs!
9.2.1.3
V
9.2.1.4
These pins are the power supplies for the analog circuitry of the ADC12B10C block.
9.3
This section provides a detailed description of all registers accessible in the ADC12B10C.
9.3.1
Figure 9-2
308
Address
0x0000
0x0001
0x0002
RH
is the high reference voltage, V
Signal Description
Memory Map and Register Definition
ATDCTL0
ATDCTL1
ATDCTL2
gives an overview on all ADC12B10C registers.
Detailed Signal Descriptions
Module Memory Map
Name
ANx (x = 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
ETRIG3, ETRIG2, ETRIG1, ETRIG0
V
V
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
RH
DDA
, V
, V
W
W
W
RL
R
R
R
SSA
ETRIGSEL
Figure 9-2. ADC12B10C Register Summary (Sheet 1 of 3)
Reserved
Bit 7
0
S12P-Family Reference Manual, Rev. 1.13
= Unimplemented or Reserved
SRES1
RL
AFFC
6
0
is the low reference voltage for ATD conversion.
ICLKSTP ETRIGLE
SRES0
5
0
NOTE
SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
4
0
ETRIGP
WRAP3
3
ETRIGE
WRAP2
2
Freescale Semiconductor
WRAP1
ASCIE
1
ACMPIE
WRAP0
Bit 0
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