S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 254
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Freescale’s Scalable Controller Area Network (S12MSCANV3)
8.2.2
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the
CAN bus:
8.2.3
A typical CAN system with MSCAN is shown in
to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current
needed for the CAN bus and has current protection against defective CAN or defective stations.
8.3
This section provides a detailed description of all registers accessible in the MSCAN.
8.3.1
Figure 8-3
register address results from the addition of base address and address offset. The base address is
determined at the MCU level and can be found in the MCU memory map description. The address offset
is defined at the module level.
The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is
determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the
first address of the module address offset.
254
Memory Map and Register Definition
0 = Dominant state
1 = Recessive state
gives an overview on all registers and their individual bits in the MSCAN memory map. The
TXCAN — CAN Transmitter Output Pin
CAN System
Module Memory Map
TXCAN
CANH
CAN Controller
Transceiver
CAN node 1
(MSCAN)
MCU
S12P-Family Reference Manual, Rev. 1.13
CANL
RXCAN
Figure 8-2. CAN System
CAN Bus
Figure
CAN node 2
8-2. Each CAN station is connected physically
CAN node n
Freescale Semiconductor
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