S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 455
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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13.4.4
Only the operations marked ‘OK’ in
Flash and Data Flash blocks. Some operations cannot be executed simultaneously because certain
hardware resources are shared by the two memories. The priority has been placed on permitting Program
Flash reads while program and erase operations execute on the Data Flash, providing read (P-Flash) while
write (D-Flash) functionality.
13.4.5
This section provides details of all available Flash commands launched by a command write sequence. The
ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following
illegal steps are performed, causing the command not to be processed by the Memory Controller:
Freescale Semiconductor
FCMD
•
•
•
0x10
0x11
0x12
Starting any command write sequence that programs or erases Flash memory before initializing the
FCLKDIV register
Writing an invalid command as part of the command write sequence
For additional possible errors, refer to the error handling table provided for each command
Allowed Simultaneous P-Flash and D-Flash Operations
Flash Command Description
Program D-Flash
Erase Verify D-
Erase D-Flash
Flash Section
Command
Sector
Table 13-30. Allowed P-Flash and D-Flash Simultaneous Operations
1. A ‘Margin Read’ is any read after executing the margin setting commands ‘Set
2. See the Note on margin settings in
3. The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase
Program Flash
Margin Read
Mass Erase
Sector Erase
User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’
level specified.
Flash Block’
Program
Read
Verify that a given number of words starting at the address provided are erased.
Program up to four words in the D-Flash block.
Erase all bytes in a sector of the D-Flash block.
(3)
(1)
S12P-Family Reference Manual, Rev. 1.13
Table 13-29. D-Flash Commands
Table 13-30
Read
Margin
Read
OK
OK
are permitted to be run simultaneously on the Program
(2)
Section 13.4.5.12
1
Function on D-Flash Memory
Data Flash
Program
OK
and
Sector
Erase
128 KByte Flash Module (S12FTMRC128K1V1)
OK
OK
Section
13.4.5.13.
Erase
Mass
OK
3
455
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