S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 207
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7.3.2.2
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the
external oscillator as reference.
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For
correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= f
2MHz range. The bits can still be written but will have no effect on the PLL filter configuration.
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking
and/or insufficient stability).
Freescale Semiconductor
0x0035
Reset
If OSCLCP is enabled (OSCE=1)
If OSCLCP is disabled (OSCE=0)
W
R
S12CPMU Reference Divider Register (CPMUREFDIV)
0
7
REFFRQ[1:0]
Write to this register clears the LOCK and UPOSC status bits.
Table 7-2. Reference Clock Frequency Selection if OSC_LCP is enabled
Figure 7-5. S12CPMU Reference Divider Register (CPMUREFDIV)
Table
0
6
7-2.
REFCLK Frequency Ranges
1MHz <= f
6MHz < f
S12P-Family Reference Manual, Rev. 1.13
2MHz < f
0
0
5
f
REF
(OSCE=1)
REF
f REF
f REF
REF
>12MHz
REF
<= 12MHz
<= 6MHz
<= 2MHz
=
=
NOTE
------------------------------------
(
f IRC1M
0
0
4
REFDIV
f OSC
S12 Clock, Reset and Power Management Unit (S12CPMU)
+
1
)
1
3
REFFRQ[1:0]
00
01
10
11
1
2
REFDIV[3:0]
1
1
REF
1
0
<=
207
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