S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 111
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Read: Anytime.
Write: Only if a transition is allowed (see
The MODC bit of the MODE register is used to select the MCU’s operating mode.
3.3.2.2
Read: Anytime
Write: anytime in special SS, writr-one in NS.
This register determines the position of the 256 Byte direct page within the memory map.It is valid for both
global and local mapping scheme.
Freescale Semiconductor
Address: 0x0011
Reset
MODC
Field
7
W
R
DP15
Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external
mode pin MODC determines the operating mode during RESET low (active). The state of the pin is registered
into the respective register bit after the RESET signal goes inactive (see
Write restrictions exist to disallow transitions between certain modes.
changes. Attempting non authorized transitions will not change the MODE bit, but it will block further writes to
the register bit except in special modes.
Write accesses to the MODE register are blocked when the device is secured.
Direct Page Register (DIRECT)
0
7
Figure 3-4. Mode Transition Diagram when MCU is Unsecured
DP14
0
6
Single-Chip
Normal
(NS)
1
S12P-Family Reference Manual, Rev. 1.13
Figure 3-5. Direct Register (DIRECT)
Table 3-5. MODE Field Descriptions
DP13
0
5
Figure
1
DP12
RESET
3-4).
0
4
1
Description
0
DP11
0
3
Single-Chip
Special
Figure 3-4
(SS)
DP10
0
Figure
0
2
Memory Map Control (S12PMMCV1)
3-4).
illustrates all allowed mode
DP9
0
1
DP8
0
0
111
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