P89CV51RD2FBC,557 NXP Semiconductors, P89CV51RD2FBC,557 Datasheet - Page 56

• Manufacturer Part Number: P89CV51RD2FBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89CV51RD2FBC,557

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: P89CV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4257; 935284103557; P89CV51RD2FBC

NXP Semiconductors
Table 48.
P89CV51RB2_RC2_RD2_3
Product data sheet
Mode
Idle
Power-down
Power-saving modes
6.12.1 Idle mode
6.12.2 Power-down mode
Initiated by
Software (Set IDL bit
in PCON)
MOV PCON, #01H
Software (Set PD bit
in PCON)
MOV PCON, #02H
6.12 Power-saving modes
The device provides two power-saving modes of operation for applications where power
consumption is critical. The two modes are Idle and Power-down; see
Idle mode is entered by setting the IDL bit in the PCON register. In Idle mode, the program
counter is stopped. The system clock continues to run and all interrupts and peripherals
remain active. The on-chip RAM and the special function registers hold their data during
this mode.
The device exits Idle mode through either a system interrupt or a hardware reset. When
exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits
Idle mode. After exiting the Interrupt Service Routine (ISR), the interrupted program
resumes execution at the instruction immediately following the instruction which invoked
the Idle mode. A hardware reset starts the device similar to a power-on reset.
The Power-down mode is entered by setting the PD bit in the PCON register. In the
Power-down mode, the clock is stopped and external interrupts are active for
level-sensitive interrupts only. SRAM contents are retained during power-down, the
minimum V
The device exits Power-down mode through either an enabled external level-sensitive
interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits
power-down. Holding an external interrupt pin LOW restarts the oscillator, the signal must
hold LOW at least 1024 clock cycles before bringing back HIGH to complete the exit.
When the interrupt signal is restored to logic V
execution resumes at the instruction immediately following the instruction which invoked
Power-down mode. A hardware reset starts the device similar to a power-on reset.
To exit properly out of power-down, the reset or external interrupt should not be executed
before the V
long enough at its normal operating level for the oscillator to restart and stabilize (normally
less than 10 ms).
DD
DD
State of MCU
CLK is running. Interrupts, serial
port and timers/counters are
active. Program counter is
stopped. ALE and PSEN signals
at a HIGH-state during Idle. All
registers remain unchanged.
CLK is stopped. On-chip SRAM
and SFR data is maintained.
ALE and PSEN signals at a
LOW-state during power-down.
External interrupts are only
active for level-sensitive
interrupts, if enabled.
level is 4.5 V.
line is restored to its normal operating voltage. Be sure to hold V
Rev. 03 — 25 August 2009
P89CV51RB2/RC2/RD2
Exited by
Enabled interrupt or hardware reset. Start of
interrupt clears IDL bit and exits Idle mode, after
the ISR RETI instruction, program resumes
execution beginning at the instruction following the
one that invoked Idle mode. A hardware reset
restarts the device similar to a power-on reset.
Enabled external level-sensitive interrupt or
hardware reset. Start of interrupt clears PD bit and
exits Power-down mode, after the ISR RETI
instruction program resumes execution beginning
at the instruction following the one that invoked
Power-down mode. A hardware reset restarts the
device similar to a power-on reset.
IH
, the interrupt service routine program
80C51 with 1 kB RAM, SPI
Table
© NXP B.V. 2009. All rights reserved.
48.
DD
voltage
56 of 76