P89CV51RD2FBC,557 NXP Semiconductors, P89CV51RD2FBC,557 Datasheet - Page 43

• Manufacturer Part Number: P89CV51RD2FBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89CV51RD2FBC,557

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: P89CV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4257; 935284103557; P89CV51RD2FBC

NXP Semiconductors
P89CV51RB2_RC2_RD2_3
Product data sheet
6.8 Watchdog timer
Table 30.
Reset source(s): any reset; reset value: 0000 0000B.
Table 31.
The WDT is intended as a recovery method in situations where the CPU may be
subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog
Timer Reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, the user
must write 01EH and 0E1H, in sequence, to the WDTRST SFR. When the WDT is
enabled, it will increment every machine cycle while the oscillator is running. There is no
Bit
Symbol
Bit
7
6
5 to 0
Fig 17. SPI transfer format with CPHA = 0
Fig 18. SPI transfer format with CPHA = 1
SCK (CPOL = 0)
SCK (CPOL = 1)
SCK (CPOL = 0)
SCK (CPOL = 1)
(for reference)
(for reference)
(from master)
(from master)
SS (to slave)
SS (to slave)
SCK cycle #
SCK cycle #
(from slave)
(from slave)
SPSR - SPI Status Register (address AAH) bit allocation
SPSR - SPI Status Register (address AAH) bit description
SPIF
Symbol
SPIF
WCOL
-
MOSI
MISO
MOSI
MISO
7
WCOL
Rev. 03 — 25 August 2009
6
Description
SPI interrupt flag. Upon completion of data transfer, this bit is set to 1.
If SPIE = 1 and ES = 1, an interrupt is then generated. This bit is
cleared by software.
Write Collision flag. Set if the SPI data register is written to during data
transfer. This bit is cleared by software.
Reserved for future use. Should be set to 0 by user programs.
MSB
MSB
MSB
MSB
1
1
2
2
6
6
5
6
6
-
3
3
5
5
P89CV51RB2/RC2/RD2
5
5
4
-
4
4
4
4
4
4
5
5
3
3
3
3
3
-
6
6
2
2
2
2
80C51 with 1 kB RAM, SPI
7
7
1
1
1
1
2
-
LSB
8
LSB
LSB
8
© NXP B.V. 2009. All rights reserved.
LSB
1
-
002aaa529
002aaa530
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0
-