P89CV51RD2FBC,557 NXP Semiconductors, P89CV51RD2FBC,557 Datasheet - Page 37

• Manufacturer Part Number: P89CV51RD2FBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89CV51RD2FBC,557

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: P89CV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4257; 935284103557; P89CV51RD2FBC

NXP Semiconductors
P89CV51RB2_RC2_RD2_3
Product data sheet
6.6.5 Framing error
Table 24.
Bit addressable; reset value: 00H.
Table 25.
Table 26.
Framing Error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. If SMOD0 = 0,
SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is set up before SMOD0
is set to 1.
Bit
Symbol
Bit
7
6
5
4
3
2
1
0
SM0, SM1
0 0
0 1
1 0
1 1
SCON - Serial port control register (address 98H) bit allocation
SCON - Serial port control register (address 98H) bit description
SCON - Serial port control register (address 98H) SM0/SM1 mode definition
SM0/FE
Symbol
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
7
UART mode
0: shift register
1: 8-bit UART
2: 9-bit UART
3: 9-bit UART
Rev. 03 — 25 August 2009
SM1
6
Description
The usage of this bit is determined by SMOD0 in the PCON register. If
SMOD0 = 0, this bit is SM0, which with SM1, defines the serial port
mode. If SMOD0 = 1, this bit is FE (Framing Error). FE is set by the
receiver when an invalid stop bit is detected. Once set, this bit cannot
be cleared by valid frames but can only be cleared by software. (Note:
It is recommended to set up UART mode bits SM0 and SM1 before
setting SMOD0 to 1.)
With SM0, defines the serial port mode; see
Enables the multiprocessor communication feature in modes 2 and 3.
In Mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the
received 9th data bit (RB8) is 0. In Mode 1, if SM2 = 1 then RI will not
be activated if a valid stop bit was not received. In Mode 0, SM2
should be 0.
Enables serial Reception. Set by software to enable reception. Clear
by software to disable reception.
The 9th data bit that will be transmitted in modes 2 and 3. Set or clear
by software as desired.
In modes 2 and 3, is the 9th data bit that was received. In mode 1, if
SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is
undefined.
Transmit Interrupt flag. Set by hardware at the end of the 8th bit time in
Mode 0, or at the stop bit in the other modes, in any serial
transmission. Must be cleared by software.
Receive Interrupt flag. Set by hardware at the end of the 8th bit time in
Mode 0, or approximately halfway through the stop bit time in all other
modes. (See SM2 for exceptions). Must be cleared by software.
SM2
5
P89CV51RB2/RC2/RD2
REN
4
TB8
Baud rate
CPU clock / 6
variable
CPU clock / 32 or CPU clock / 16
variable
3
80C51 with 1 kB RAM, SPI
RB8
2
Table
© NXP B.V. 2009. All rights reserved.
26.
TI
1
37 of 76
RI
0