P89CV51RD2FBC,557 NXP Semiconductors, P89CV51RD2FBC,557 Datasheet - Page 26

• Manufacturer Part Number: P89CV51RD2FBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89CV51RD2FBC,557

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: P89CV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4257; 935284103557; P89CV51RD2FBC

NXP Semiconductors
P89CV51RB2_RC2_RD2_3
Product data sheet
6.4 Timers/counters 0 and 1
Table 12.
The two 16-bit timer/counter registers: Timer 0 and Timer 1 can be configured to operate
either as timers or event counters (see
In the ‘Timer’ function, the register is incremented every machine cycle. Thus, one can
think of it as counting machine cycles. Since a machine cycle consists of six oscillator
periods, the count rate is
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once every machine cycle.
When the samples show a HIGH in one cycle and a LOW in the next cycle, the count is
incremented. The new count value appears in the register in the machine cycle following
the one in which the transition was detected. Since it takes two machine cycles
(12 oscillator periods) for a 1-to-0 transition to be recognized, the maximum count rate is
1
input signal, but to ensure that a given level is sampled at least once before it changes, it
should be held for at least one full machine cycle. In addition to the ‘Timer’ or ‘Counter’
selection, Timer 0 and Timer 1 have four selectable operating modes.
IAP function
Program status bit, boot vector,
6 /12 bit
Read security bits, status bit, boot
vector
Erase page
12
of the oscillator frequency. There are no restrictions on the duty cycle of the external
IAP function calls
Rev. 03 — 25 August 2009
1
6
of the oscillator frequency.
…continued
IAP call parameters
Input parameters:
R1 = 06H or 86H (WDT feed)
DPL = 00H = program status bit
DPL = 01H = program boot vector
DPL = 02H = 6 /12 bit
ACC = boot vector value to program
Return parameter(s):
ACC = 00: pass
ACC is not 00: fail
Input parameters:
ACC = 07H or 87H (WDT feed)
DPL = 00H = security bits
DPL = 01H = status bit
DPL = 02H = boot vector
Return parameter(s):
ACC = 00 SoftICE S/N-match 0 SB 0 DBL_CLK
Input parameters:
R1 = 08H or 88H (WDT feed)
DPH = page address high byte
DPL = page address low byte
Return parameter(s):
ACC = 00: pass
ACC is not 00: fail
Table 13
P89CV51RB2/RC2/RD2
and
Table
14).
80C51 with 1 kB RAM, SPI
© NXP B.V. 2009. All rights reserved.
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