ATSAM3U2EA-AU Atmel, ATSAM3U2EA-AU Datasheet - Page 948
![IC MCU 32BIT 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
ATSAM3U2EA-AU
Manufacturer Part Number
ATSAM3U2EA-AU
Description
IC MCU 32BIT 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2EA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Controller Family/series
SAM3U
No. Of I/o's
96
Ram Memory Size
36KB
Cpu Speed
96MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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39.6.4
39.6.5
948
948
SAM3U Series
SAM3U Series
USB V2.0 High Speed BUS Transactions
Endpoint Configuration
Each transfer results in one or more transactions over the USB bus.
There are five kinds of transactions flowing across the bus in packets:
Figure 39-3. Control Read and Write Sequences
A status IN or OUT transaction is identical to a data IN or OUT transaction.
The endpoint 0 is always a control endpoint, it must be programmed and active in order to be
enabled when the End Of Reset interrupt occurs.
To configure the endpoints:
Note: For control endpoints the direction has no effect.
Control endpoints can generate interrupts and use only 1 bank.
1. Setup Transaction
2. Data IN Transaction
3. Data OUT Transaction
4. Status IN Transaction
5. Status OUT Transaction
• Fill the configuration register (UDPHS_EPTCFG) with the endpoint size, direction (IN or
• Fill the number of transactions (NB_TRANS) for isochronous endpoints.
• Verify that the EPT_MAPD flag is set. This flag is set if the endpoint size and the number of
• Configure control flags of the endpoint and enable it in UDPHS_EPTCTLENBx according to
OUT), type (CTRL, Bulk, IT, ISO) and the number of banks.
banks are correct compared to the FIFO maximum capacity and the maximum number of
allowed banks.
“UDPHS Endpoint Control Register” on page
Control Write
Control Read
No Data
Control
Setup Stage
Setup Stage
Setup Stage
Setup TX
Setup TX
Setup TX
Status Stage
Status IN TX
Data OUT TX
Data IN TX
Data Stage
Data Stage
993.
Data OUT TX
Data IN TX
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Status OUT TX
Status Stage
Status Stage
Status IN TX
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