ATSAM3U2EA-AU Atmel, ATSAM3U2EA-AU Datasheet - Page 823
![IC MCU 32BIT 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
ATSAM3U2EA-AU
Manufacturer Part Number
ATSAM3U2EA-AU
Description
IC MCU 32BIT 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2EA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Controller Family/series
SAM3U
No. Of I/o's
96
Ram Memory Size
36KB
Cpu Speed
96MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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6430D–ATARM–25-Mar-11
h. Program LLI_W(n).DMAC_CTRLBx with the following field’s values:
i.
j.
k. Program the channel registers in the Memory for the second descriptor. This
l.
m. The LLI_B(n).DMAC_DADDRx is not relevant if previous word aligned descriptor
n. Program LLI_B(n).DMAC_CTRLAx with the following field’s values:
o. Program LLI_B(n).DMAC_CTRLBx with the following field’s values:
– DST_INCR is set to INCR.
– SRC_INCR is set to INCR.
– FC field is programmed with peripheral to memory flow control mode.
– Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next
– DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
p. Program LLI_B(n).DMAC_CFGx memory location for channel x with the following
– FIFOCFG defines the watermark of the DMAC channel FIFO.
– SRC_H2SEL is set to true to enable hardware handshaking on the destination.
descriptor location points to 0.
DMA Controller is able to prefetch data and write HSMCI simultaneously.
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC).
–DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
Program LLI_W(n).DMAC_CFGx register for channel x with the following field’s
values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Address are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
Program LLI_W(n).DMAC_DSCRx with the address of LLI_B(n) descriptor. And set
the DSCRx_IF to the AHB Layer ID. This operation actually links the Word oriented
descriptor on the second byte oriented descriptor. When block_length[1:0] is equal
to 0 (multiple of 4) LLI_W(n).DMAC_DSCRx points to 0, only LLI_W(n) is relevant.
descriptor will be byte oriented. This descriptor is referred to as LLI_B(n), standing
for LLI Byte oriented.
The LLI_B(n).DMAC_SADDRx field in memory must be set with the starting
address of the HSMCI_FIFO address.
was enabled. If 1, 2 or 3 bytes are transferred, that address is user defined and not
word aligned.
–DST_WIDTH is set to BYTE.
–SRC_WIDTH is set to BYTE.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer).
field’s values:
DMA Controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
SAM3U Series
823
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