ATSAM3U2EA-AU Atmel, ATSAM3U2EA-AU Datasheet - Page 27
![IC MCU 32BIT 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
ATSAM3U2EA-AU
Manufacturer Part Number
ATSAM3U2EA-AU
Description
IC MCU 32BIT 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2EA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Controller Family/series
SAM3U
No. Of I/o's
96
Ram Memory Size
36KB
Cpu Speed
96MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7.4
7.5
Table 7-3.
6430D–ATARM–25-Mar-11
Slaves
0
1
2
3
4
5
6
7
8
9
Matrix Slaves
Master to Slave Access
USB Device High Speed Dual Port RAM (DPR)
SAM3U Master to Slave Access
High Speed Peripheral Bridge
Low Speed Peripheral Bridge
NAND Flash Controller RAM
External Bus Interface
Internal SRAM0
Internal SRAM1
Internal Flash 0
Internal Flash 1
Internal ROM
The Bus Matrix of the SAM3U manages 10 slaves. Each slave has its own arbiter, allowing a dif-
ferent arbitration per slave.
Table 7-2.
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the USB Device High speed DMA to the Internal Peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “–” in
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
Slave 8
Slave 9
List of Bus Matrix Slaves
Masters
Internal SRAM0
Internal SRAM1
Internal ROM
Internal Flash 0
Internal Flash 1
USB Device High Speed Dual Port RAM (DPR)
NAND Flash Controller RAM
External Bus Interface
Low Speed Peripheral Bridge
High Speed Peripheral Bridge
Cortex-M3
I/D Bus
X
X
X
0
–
–
–
–
–
–
–
Cortex-M3 S
Bus
X
X
X
X
X
X
X
1
–
–
–
PDC
X
X
X
X
X
X
X
2
–
–
–
SAM3U Series
USB Device
High Speed
DMA
Table 7-3
X
X
X
–
X
X
3
–
–
–
–
below.
Controller
DMA
4
X
X
X
–
–
–
X
X
–
–
27
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