ATSAM3U2EA-AU Atmel, ATSAM3U2EA-AU Datasheet - Page 750

• Manufacturer Part Number: ATSAM3U2EA-AU
• Description: IC MCU 32BIT 128KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U2EA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b, 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Controller Family/series: SAM3U
• No. Of I/o's: 96
• Ram Memory Size: 36KB
• Cpu Speed: 96MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 36 KB
• Interface Type: 4xUSART, 2xTWI, 5xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

35.8.15
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• TX_PL: Transmitter Preamble Length
0: The Transmitter Preamble pattern generation is disabled
1 - 15: The Preamble Length is TX_PL x Bit Period
• TX_PP: Transmitter Preamble Pattern
The following values assume that TX_MPOL field is not set:
• TX_MPOL: Transmitter Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled
1 - 15: The detected preamble length is RX_PL x Bit Period
750
750
Value
31
23
15
–
–
–
7
–
00
01
10
11
SAM3U Series
SAM3U Series
USART Manchester Configuration Register
Name
ALL_ONE
ALL_ZERO
ZERO_ONE
ONE_ZERO
DRIFT
30
22
14
US_MAN
0x40090050 (0), 0x40094050 (1), 0x40098050 (2), 0x4009C050 (3)
Read-write
–
–
6
–
Description
The preamble is composed of ‘1’s
The preamble is composed of ‘0’s
The preamble is composed of ‘01’s
The preamble is composed of ‘10’s
29
21
13
1
–
–
5
–
RX_MPOL
TX_MPOL
28
20
12
–
4
–
“USART Write Protect Mode Register” on page
27
19
11
–
–
3
26
18
10
–
–
2
RX_PL
TX_PL
25
17
9
1
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
RX_PP
TX_PP
752.
24
16
8
0