ATSAM3U2EA-AU Atmel, ATSAM3U2EA-AU Datasheet - Page 227
![IC MCU 32BIT 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
ATSAM3U2EA-AU
Manufacturer Part Number
ATSAM3U2EA-AU
Description
IC MCU 32BIT 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2EA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Controller Family/series
SAM3U
No. Of I/o's
96
Ram Memory Size
36KB
Cpu Speed
96MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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6430D–ATARM–25-Mar-11
A debugging system that includes a program, used to detect, locate, and correct software faults,
together with custom hardware that supports software debugging.
Direct Memory Access (DMA)
An operation that accesses main memory directly, without the processor performing any
accesses to the data concerned.
Doubleword
A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise
stated.
Doubleword-aligned
A data item having a memory address that is divisible by eight.
Endianness
Byte ordering. The scheme that determines the order that successive bytes of a data word are
stored in memory. An aspect of the system’s memory mapping.
See also
Exception
An event that interrupts program execution. When an exception occurs, the processor suspends
the normal program flow and starts execution at the address indicated by the corresponding
exception vector. The indicated address contains the first instruction of the handler for the
exception.
An exception can be an interrupt request, a fault, or a software-generated system exception.
Faults include attempting an invalid memory access, attempting to execute an instruction in an
invalid processor state, and attempting to execute an undefined instruction.
Exception service routine
See
Exception vector
See
Flat address mapping
A system of organizing memory in which each physical address in the memory space is the
same as the corresponding virtual address.
Halfword
A 16-bit data item.
Illegal instruction
An instruction that is architecturally Undefined.
Implementation-defined
The behavior is not architecturally defined, but is defined and documented by individual
implementations.
Implementation-specific
“Interrupt
“Interrupt
“Little-endian (LE)”
handler”.
vector”.
SAM3U Series
227
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