ATSAM3U2EA-AU Atmel, ATSAM3U2EA-AU Datasheet - Page 291
![IC MCU 32BIT 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
ATSAM3U2EA-AU
Manufacturer Part Number
ATSAM3U2EA-AU
Description
IC MCU 32BIT 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2EA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Controller Family/series
SAM3U
No. Of I/o's
96
Ram Memory Size
36KB
Cpu Speed
96MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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19.3.6.2
Figure 19-6. NRSTB Reset
Note:
19.3.6.3
19.3.7
19.3.7.1
6430D–ATARM–25-Mar-11
32 kHz Low Power Crystal
perih_nreset, ice_reset and proc_nreset are not shown, but are asserted low thanks to the vddcore_nreset signal controlling the
Reset controller.
SHDN / vr_standby
Core Reset
Oscillator output
vddcore_nreset
NRSTB Asynchronous Reset Pin
SHDN output pin
Supply Monitor Reset
bodcore_in
NRSTB
The NRSTB pin is an asynchronous reset input, which acts exactly like the zero-power power-on
reset cell.
As soon as NRSTB is tied to GND, the supply controller is reset generating in turn, a reset of the
whole system.
When NRSTB is released, the system can start as described in
Backup Power
The NRSTB pin does not need to be driven during power-up phase to allow a reset of the sys-
tem, it is done by the zero-power power-on cell.
As shown in
the SHDN pin to control external voltage regulator with shutdown capabilities.
The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described
previously in
mally asserted before shutting down the core power supply and released as soon as the core
power supply is correctly regulated.
There are two additional sources which can be programmed to activate vddcore_nreset:
The supply monitor is capable of generating a reset of the system. This can be enabled by set-
ting the SMRSTEN bit in the Supply Controller Supply Monitor Mode Register (SUPC_SMMR).
If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is imme-
diately activated for a minimum of 1 slow clock cycle.
• a supply monitor detection
• a brownout detection
Figure
Section 19.3.6 ”Backup Power Supply
Supply”.
19-6, the SHDN pin acts like the vr_standby signal making it possible to use
30 Slow Clock Cycles = about 1ms
Reset”. The vddcore_nreset signal is nor-
between 2 and 3 Slow Clock Cycles
Section 19.3.6.1 ”Raising the
SAM3U Series
291
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