ATSAM3U2EA-AU Atmel, ATSAM3U2EA-AU Datasheet - Page 179
![IC MCU 32BIT 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
ATSAM3U2EA-AU
Manufacturer Part Number
ATSAM3U2EA-AU
Description
IC MCU 32BIT 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2EA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Controller Family/series
SAM3U
No. Of I/o's
96
Ram Memory Size
36KB
Cpu Speed
96MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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13.19.10 NVIC design hints and tips
13.19.10.1
6430D–ATARM–25-Mar-11
NVIC programming hints
Ensure software uses correctly aligned register accesses. The processor does not support
unaligned accesses to NVIC registers. See the individual register descriptions for the supported
access sizes.
A interrupt can enter pending state even it is disabled.
Before programming VTOR to relocate the vector table, ensure the vector table entries of the
new vector table are setup for fault handlers and all enabled exception like interrupts. For more
information see
Software uses the CPSIE I and CPSID I instructions to enable and disable interrupts. The
CMSIS provides the following intrinsic functions for these instructions:
In addition, the CMSIS provides a number of functions for NVIC control, including:
Table 13-29. CMSIS functions for NVIC control
For more information about these functions see the CMSIS documentation.
CMSIS interrupt control function
void NVIC_SetPriorityGrouping(uint32_t
priority_grouping)
void NVIC_EnableIRQ(IRQn_t IRQn)
void NVIC_DisableIRQ(IRQn_t IRQn)
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
void NVIC_SetPendingIRQ (IRQn_t IRQn)
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
uint32_t NVIC_GetActive (IRQn_t IRQn)
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
uint32_t NVIC_GetPriority (IRQn_t IRQn)
void NVIC_SystemReset (void)
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
“Vector Table Offset Register” on page
Return true if IRQn is pending
Set priority for IRQn
Read priority of IRQn
Description
Set the priority grouping
Enable IRQn
Disable IRQn
Set IRQn pending
Clear IRQn pending status
Return the IRQ number of the active
interrupt
Reset the system
186.
SAM3U Series
179
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