ATMEGA32-16AU Atmel, ATMEGA32-16AU Datasheet - Page 276

• Manufacturer Part Number: ATMEGA32-16AU
• Description: IC AVR MCU 32K 16MHZ 5V 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PROG_COMMANDS
($5)
PROG_PAGELOAD
($6)
PROG_PAGEREAD
($7)
Data Registers
2503Q–AVR–02/11
The AVR specific public JTAG instruction for entering programming commands via the JTAG
port. The 15-bit Programming Command Register is selected as Data Register. The active
states are the following:
•
•
•
•
The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.
The 1024 bit Virtual Flash Page Load Register is selected as Data Register. This is a virtual
scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register
is 8-bit. Unlike most JTAG instructions, the Update-DR state is not used to transfer data from the
Shift Register. The data are automatically transferred to the Flash page buffer byte by byte in the
Shift-DR state by an internal state machine. This is the only active state:
•
Note:
The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port.
The 1032 bit Virtual Flash Page Read Register is selected as Data Register. This is a virtual
scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift
Register is 8-bit. Unlike most JTAG instructions, the Capture-DR state is not used to transfer
data to the Shift Register. The data are automatically transferred from the Flash page buffer byte
by byte in the Shift-DR state by an internal state machine. This is the only active state:
•
Note:
The Data Registers are selected by the JTAG Instruction Registers described in section
gramming Specific JTAG Instructions” on page
programming operations are:
•
•
•
•
•
Capture-DR: The result of the previous command is loaded into the Data Register.
Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the
previous command and shifting in the new command.
Update-DR: The programming command is applied to the Flash inputs
Run-Test/Idle: One clock cycle is generated, executing the applied command (not always
required, see
Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically
loaded into the Flash page one byte at a time.
Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the
TCK input. The TDI input is ignored.
Reset Register
Programming Enable Register
Programming Command Register
Virtual Flash Page Load Register
Virtual Flash Page Read Register
The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in
JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise program-
ming algorithm must be used.
The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first device in
JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise program-
ming algorithm must be used.
Table 116
below).
274. The Data Registers relevant for
ATmega32(L)
“Pro-
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