ATMEGA32-16AU Atmel, ATMEGA32-16AU Datasheet - Page 108
![IC AVR MCU 32K 16MHZ 5V 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA32-16AU
Manufacturer Part Number
ATMEGA32-16AU
Description
IC AVR MCU 32K 16MHZ 5V 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
3
Rohs Compliant
Yes
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32-16AU
Manufacturer:
ATMEL
Quantity:
20 000
2503Q–AVR–02/11
Table 45. Compare Output Mode, Fast PWM
Note:
Table 46
rect or the phase and frequency correct, PWM mode.
Table 46. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
Note:
• Bit 3 – FOC1A: Force Output Compare for Compare unit A
• Bit 2 – FOC1B: Force Output Compare for Compare unit B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x1:0 bits that determine the effect of the forced compare.
COM1A1/COM1B1
COM1A1/COM1B1
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set.
shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase cor-
0
0
1
1
0
0
1
1
this case the compare match is ignored, but the set or clear is done at BOTTOM.
PWM Mode” on page 99.
“Phase Correct PWM Mode” on page 101.
COM1A0/COM1B0
COM1A0/COM1B0
0
1
0
1
0
1
0
1
for more details.
Description
Normal port operation, OC1A/OC1B
disconnected.
WGM13:0 = 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port
operation).
For all other WGM13:0 settings, normal port
operation, OC1A/OC1B disconnected.
Clear OC1A/OC1B on compare match, set
OC1A/OC1B at BOTTOM,
(non-inverting mode)
Set OC1A/OC1B on compare match, clear
OC1A/OC1B at BOTTOM,
(inverting mode)
Description
Normal port operation, OC1A/OC1B
disconnected.
WGM13:0 = 9 or 14: Toggle OC1A on
Compare Match, OC1B disconnected (normal
port operation).
For all other WGM13:0 settings, normal port
operation, OC1A/OC1B disconnected.
Clear OC1A/OC1B on compare match when
up-counting. Set OC1A/OC1B on compare
match when downcounting.
Set OC1A/OC1B on compare match when up-
counting. Clear OC1A/OC1B on compare
match when downcounting.
(1)
for more details.
ATmega32(L)
See “Fast
(1)
108
See