ATMEGA32-16AU Atmel, ATMEGA32-16AU Datasheet - Page 222
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ATMEGA32-16AU
Manufacturer Part Number
ATMEGA32-16AU
Description
IC AVR MCU 32K 16MHZ 5V 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
3
Rohs Compliant
Yes
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32-16AU
Manufacturer:
ATMEL
Quantity:
20 000
Using the
Boundary-scan
Chain
Using the On-chip
Debug System
2503Q–AVR–02/11
•
•
•
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting
JTAG instruction and using Data Registers, and some JTAG instructions may select certain
functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.
Note:
For detailed information on the JTAG specification, refer to the literature listed in
on page
A complete description of the Boundary-scan capabilities are given in the section
(JTAG) Boundary-scan” on page
As shown in
•
•
•
All read or modify/write operations needed for implementing the Debugger are done by applying
AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O
memory mapped location which is part of the communication interface between the CPU and the
JTAG system.
The Break Point Unit implements Break on Change of Program Flow, Single Step Break, 2 Pro-
gram Memory Break Points, and 2 combined Break Points. Together, the 4 Break Points can be
configured as either:
•
•
•
•
•
on the TDO pin. The JTAG Instruction selects a particular Data Register as path between
TDI and TDO and controls the circuitry surrounding the selected Data Register.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is
latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-
IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift
Data Register – Shift-DR state. While in this state, upload the selected Data Register
(selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI
input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must
be held low during input of all bits except the MSB. The MSB of the data is shifted in when
this state is left by setting TMS high. While the Data Register is shifted in from the TDI pin,
the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the
TDO pin.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data
Register has a latched parallel-output, the latching takes place in the Update-DR state. The
Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.
A scan chain on the interface between the internal AVR CPU and the internal peripheral
units
Break Point unit
Communication interface between the CPU and JTAG system
4 single Program Memory Break Points
3 Single Program Memory Break Point + 1 single Data Memory Break Point
2 single Program Memory Break Points + 2 single Data Memory Break Points
2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range
Break Point”)
2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range
Break Point”)
Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS high for five TCK clock periods.
224.
Figure
112, the hardware support for On-chip Debugging consists mainly of:
225.
ATmega32(L)
“Bibliography”
“IEEE 1149.1
222