ATMEGA16U4-AU Atmel, ATMEGA16U4-AU Datasheet - Page 324

• Manufacturer Part Number: ATMEGA16U4-AU
• Description: MCU AVR 16K FLASH USB 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16U4-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.5.2
26.6
26.6.1
7766F–AVR–11/10
Boundary-scan Chain
MCU Status Register – MCUSR
Scanning the Digital Port Pins
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connection.
Figure 26-3
disabled during Boundary-scan when the JTAG IC contains EXTEST or SAMPLE_PRELOAD.
The cell consists of a bi-directional pin cell that combines the three signals Output Control -
OCxn, Output Data - ODxn, and Input Data - IDxn, into only a two-stage Shift Register. The port
and pin indexes are not used in the following description
The Boundary-scan logic is not included in the figures in the datasheet.
simple digital port pin as described in the section
details from
When no alternate port function is present, the Input Data - ID - corresponds to the PINxn Regis-
ter value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output
Control corresponds to the Data Direction - DD Register, and the Pull-up Enable - PUExn - cor-
responds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in
scan chain read the actual pin value. For analog function, there is a direct connection from the
external pin to the analog circuit. There is no scan chain on the interface between the digital and
the analog circuitry, but some digital control signal to analog circuitry are turned off to avoid driv-
ing contention on the pads.
When JTAG IR contains EXTEST or SAMPLE_PRELOAD the clock is not sent out on the port
pins even if the CKOUT fuse is programmed. Even though the clock is output when the JTAG IR
contains SAMPLE_PRELOAD, the clock is not sampled by the boundary scan.
Bit
Read/Write
Initial Value
Figure 26-3
shows the Boundary-scan Cell for a bi-directional port pin. The pull-up function is
7
–
R
0
6
–
R
0
replaces the dashed box in
5
–
R
0
4
JTRF
R/W
See Bit Description
3
WDRF
R/W
“I/O-Ports” on page
Figure
2
BORF
R/W
26-4.
1
EXTRF
R/W
ATmega16/32U4
Figure 26-4
65. The Boundary-scan
0
PORF
R/W
Figure 26-4
MCUSR
to make the
shows a
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