ATMEGA16U4-AU Atmel, ATMEGA16U4-AU Datasheet - Page 288

• Manufacturer Part Number: ATMEGA16U4-AU
• Description: MCU AVR 16K FLASH USB 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16U4-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7766F–AVR–11/10
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - BYCT10:8 - Byte count (high) Bits
Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. The LSB part is
provided by the UEBCLX register.
• 7-0 - BYCT7:0 - Byte Count (low) Bits
Set by the hardware. BYCT10:0 is:
- (for IN endpoint) increased after each writing into the endpoint and decremented after each
byte sent,
- (for OUT endpoint) increased after each byte sent by the host, and decremented after each
byte read by the software.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - EPINT6:0 - Endpoint Interrupts Bits
Set by hardware when an interrupt is triggered by the UEINTX register and if the corresponding
endpoint interrupt enable bit is set.
Cleared by hardware when the interrupt source is served.
Bit
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Read/Write
-
BYCT D7
R
7
0
R
-
R
7
0
7
0
EPINT D6
-
BYCT D6
R
R
6
0
6
0
R
6
0
-
EPINT D5
BYCT D5
R
5
0
R
5
0
R
5
0
-
EPINT D4
BYCT D4
R
4
0
R
4
0
R
4
0
-
EPINT D3
BYCT D3
R
3
0
R
3
0
R
3
0
BYCT D10 BYCT D9
EPINT D2
BYCT D2
R
2
0
ATmega16/32U4
R
2
0
R
2
0
EPINT D1
BYCT D1
1
R
0
R
R
1
0
1
0
BYCT D8
EPINT D0 UEINT
BYCT D0 UEBCLX
R
0
0
R
R
0
0
0
0
UEBCHX
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