ATMEGA16U4-AU Atmel, ATMEGA16U4-AU Datasheet - Page 209

• Manufacturer Part Number: ATMEGA16U4-AU
• Description: MCU AVR 16K FLASH USB 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16U4-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.10.5
18.10.6
18.11 Examples of Baud Rate Setting
7766F–AVR–11/10
USART Control and Status Register n D– UCSRnD
USART Baud Rate Registers – UBRRLn and UBRRHn
• Bits 7:2 – Reserved bits
These bits are reserved and will be read as ‘0’. Do not set these bits.
• Bits 1 – CTSEN: UART CTS Signal Enable
Set this bit by firmware to enable the transmission flow control signal (CTS). Transmission will
be enabled only if CTS input = 0. Clear this bit to disable the transmission flow control signal.
Transmission will occur without hardware condition. Data Direction Register bit must be correctly
clear to enable the pin as an input.
• Bits 0 – RTSEN: UART RTS Signal Enable
Set this bit by firmware to enable the reception flow control signal (RTS). In this case the RTS
line will automatically rise when the FIFO is full. Clear this bit to disable the reception flow control
signal. Data Direction Register bit must be correctly set to enable the pin as an output.
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four
most significant bits, and the UBRRL contains the eight least significant bits of the USART baud
rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is
changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.
For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-
chronous operation can be generated by using the UBRR settings in
UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate,
are bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
7
R/W
0
15
UBRR[7:0]
7
R
R/W
0
0
–
–
6
R/W
0
14
6
R
R/W
0
0
–
–
13
5
R
R/W
0
0
R/W
5
0
–
–
12
4
R
R/W
0
0
R/W
4
0
–
–
11
UBRR[11:8]
3
R/W
R/W
0
0
3
R/W
0
–
10
2
R/W
R/W
0
0
2
R/W
0
–
9
1
R/W
R/W
0
0
1
CTSEN
R/W
0
ATmega16/32U4
Table 18-9
8
0
R/W
R/W
0
0
0
RTSEN
R/W
0
UBRRHn
UBRRLn
to
UCSRnD
Table
18-12.
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