ATMEGA16U4-AU Atmel, ATMEGA16U4-AU Datasheet - Page 142

• Manufacturer Part Number: ATMEGA16U4-AU
• Description: MCU AVR 16K FLASH USB 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16U4-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3
15.3.1
7766F–AVR–11/10
Counter Unit
Counter Initialization for Asynchronous Mode
The main part of the Timer/Counter4 is the programmable bi-directional counter unit.
3
Figure 15-3. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
asynchronous PLL clock using the Clock Select bits (CS4<3:0>) and the PLL Postscaler for High
Speed Timer bits (PLLTM1:0). When no clock source is selected (CS4<3:0> = 0) the timer is
stopped. However, the TCNT4 value can be accessed by the CPU, regardless of whether clk
is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence of the Timer/Counter4 is determined by the setting of the WGM10 and
PWM4x bits located in the Timer/Counter4 Control Registers (TCCR4A, TCCR4C and
TCCR4D). For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page
the mode of operation selected by the PWM4x and WGM40 bits. The Overflow Flag can be used
for generating a CPU interrupt.
To change Timer/Counter4 to the asynchronous mode follow the procedure below:
shows a block diagram of the counter and its surroundings.
1. Enable PLL.
2. Wait 100µs for PLL to stabilize .
3. Poll the PLOCK bit until it is set.
4. Configure the PLLTM1:0 bits in the PLLFRQ register to enable the asynchronous mode
(different from 0:0 value).
count
direction
clear
clk
top
bottom
Tn
DATA BUS
TCNT4
T4
). The timer clock is generated from an synchronous system clock or an
TCNT4 increment or decrement enable.
Select between increment and decrement.
Clear TCNT4 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT4 has reached maximum value.
Signalize that TCNT4 has reached minimum value (zero).
149. The Timer/Counter Overflow Flag (TOV4) is set according to
direction
count
clear
clk
T4
bottom
Control Logic
top
TOV4
ATmega16/32U4
T4
PLLTM1:0
PCK
Timer/Counter4 Count Enable
( From Prescaler )
CK
in the following.
Figure 15-
142
T1