HD64F3672FXV Renesas Electronics America, HD64F3672FXV Datasheet - Page 63

IC H8/3672 MCU FLASH 48LQFP

HD64F3672FXV

Manufacturer Part Number
HD64F3672FXV
Description
IC H8/3672 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheets

Specifications of HD64F3672FXV

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
48-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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1. When the BSET instruction is executed, first the CPU reads port 5.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET.
Input/output
Pin state
PCR5
PDR5
Input/output
Pin state
PCR5
PDR5
BSET
Prior to executing BSET instruction
BSET instruction executed instruction
After executing BSET instruction
Description on operation
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level
signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem,
store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the
data in the work area, then write this data to PDR5.
#0,
P57
Input
Low
level
0
1
P57
Input
Low
level
0
0
@PDR5
0
0
P56
Input
High
level
0
1
P56
Input
High
level
P55
Output
Low
level
1
0
P55
Output
Low
level
1
0
The BSET instruction is executed for port 5.
P54
Output
Low
level
1
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P53
Output
Low
level
1
0
Rev.4.00 Nov. 02, 2005 Page 37 of 304
P52
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P51
1
0
Output
Low
level
REJ09B0143-0400
Section 2 CPU
P50
Output
High
level
1
1
P50
Output
Low
level
1
0

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