HD64F3672FXV Renesas Electronics America, HD64F3672FXV Datasheet - Page 19

• Manufacturer Part Number: HD64F3672FXV
• Description: IC H8/3672 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FXV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 48-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview
Figure 1.1 Internal Block Diagram ................................................................................................. 2
Figure 1.2 Pin Arrangement (FP-64E)............................................................................................ 3
Figure 1.3 Pin Arrangement (FP-48F, FP-48B).............................................................................. 4
Section 2 CPU
Figure 2.1 Memory Map................................................................................................................. 8
Figure 2.2 CPU Registers ............................................................................................................... 9
Figure 2.3 Usage of General Registers ......................................................................................... 10
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 11
Figure 2.5 General Register Data Formats (1).............................................................................. 13
Figure 2.5 General Register Data Formats (2).............................................................................. 14
Figure 2.6 Memory Data Formats................................................................................................. 15
Figure 2.7 Instruction Formats...................................................................................................... 26
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 30
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 32
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 33
Figure 2.11 CPU Operation States................................................................................................ 34
Figure 2.12 State Transitions ........................................................................................................ 35
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 49
Figure 3.2 Stack Status after Exception Handling ........................................................................ 51
Figure 3.3 Interrupt Sequence....................................................................................................... 52
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 53
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 55
Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 59
Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 60
Figure 4.3 Operation when Condition is not Satisfied in Branch Instruction ............................... 61
Figure 4.4 Operation when Another Interrupt is Accepted at Address Break
Figure 4.5 Operation when the Instruction Set is not Executed and does not
Setting Instruction ....................................................................................................... 62
Branch due to Conditions not Being Satisfied............................................................. 63
Same Address............................................................................................................ 36
Figures
Rev.4.00 Nov. 02, 2005 Page xvii of xxiv