HD64F3672FXV Renesas Electronics America, HD64F3672FXV Datasheet - Page 21

• Manufacturer Part Number: HD64F3672FXV
• Description: IC H8/3672 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FXV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 48-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 11.2 Free-Running Counter Operation ............................................................................ 142
Figure 11.3 Periodic Counter Operation..................................................................................... 143
Figure 11.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 143
Figure 11.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 144
Figure 11.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 144
Figure 11.7 Input Capture Operating Example........................................................................... 145
Figure 11.8 Buffer Operation Example (Input Capture)............................................................. 146
Figure 11.9 PWM Mode Example (1) ........................................................................................ 147
Figure 11.10 PWM Mode Example (2) ...................................................................................... 147
Figure 11.11 Buffer Operation Example (Output Compare) ...................................................... 148
Figure 11.12 PWM Mode Example
Figure 11.13 PWM Mode Example
Figure 11.14 Count Timing for Internal Clock Source ............................................................... 151
Figure 11.15 Count Timing for External Clock Source.............................................................. 151
Figure 11.16 Output Compare Output Timing ........................................................................... 152
Figure 11.17 Input Capture Input Signal Timing........................................................................ 152
Figure 11.18 Timing of Counter Clearing by Compare Match................................................... 153
Figure 11.19 Buffer Operation Timing (Compare Match).......................................................... 153
Figure 11.20 Buffer Operation Timing (Input Capture) ............................................................. 154
Figure 11.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 154
Figure 11.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 155
Figure 11.23 Timing of Status Flag Clearing by CPU................................................................ 155
Figure 11.24 Contention between TCNT Write and Clear ......................................................... 156
Figure 11.25 Internal Clock Switching and TCNT Operation.................................................... 157
Figure 11.26 When Compare Match and Bit Manipulation Instruction to TCRW
Section 12 Watchdog Timer
Figure 12.1 Block Diagram of Watchdog Timer ........................................................................ 159
Figure 12.2 Watchdog Timer Operation Example...................................................................... 162
Section 13 Serial Communication Interface 3 (SCI3)
Figure 13.1 Block Diagram of SCI3 ........................................................................................... 164
Figure 13.2 Data Format in Asynchronous Communication ...................................................... 177
Figure 13.3 Relationship between Output Clock and Transfer Data Phase
Figure 13.4 Sample SCI3 Initialization Flowchart ..................................................................... 178
Figure 13.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 177
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 179
(TOB, TOC, and TOD = 0: initial output values are set to 0) ............................... 149
(TOB, TOC, and TOD = 1: initial output values are set to 1) ............................... 150
Occur at the Same Timing..................................................................................... 158
Rev.4.00 Nov. 02, 2005 Page xix of xxiv