HD64F3672FXV Renesas Electronics America, HD64F3672FXV Datasheet - Page 235

• Manufacturer Part Number: HD64F3672FXV
• Description: IC H8/3672 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FXV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 48-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. When changing the operating mode or analog input
channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The
ADST bit can be set at the same time as the operating mode or analog input channel is changed.
14.4.1
In single mode, A/D conversion is performed once for the analog input on the specified single
channel as follows:
1. A/D conversion is started from the first channel when the ADST bit in ADCSR is set to 1,
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST
14.4.2
In scan mode, A/D conversion is performed sequentially for the analog input on the specified
channels (four channels maximum) as follows:
1. When the ADST bit is set to 1 by software, or external trigger input, A/D conversion starts on
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1.
4. The ADST bit is not automatically cleared to 0. Steps [2] to [3] are repeated as long as the
according to software or external trigger input.
register to the channel.
this time, an ADI interrupt request is generated.
bit is automatically cleared to 0 and the A/D converter enters the wait state.
the first channel in the group.
the A/D data register corresponding to each channel.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first
channel in the group starts again.
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
Operation
Single Mode
Scan Mode
Rev.4.00 Nov. 02, 2005 Page 209 of 304
Section 14 A/D Converter
REJ09B0143-0400