HD64F3672FXV Renesas Electronics America, HD64F3672FXV Datasheet - Page 218

• Manufacturer Part Number: HD64F3672FXV
• Description: IC H8/3672 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FXV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 48-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface 3 (SCI3)
Rev.4.00 Nov. 02, 2005 Page 192 of 304
REJ09B0143-0400
Figure 13.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Yes
No
No
Clear TE and RE bits in SCR to 0
Start transmission/reception
Write transmit data to TDR
Read receive data in RDR
Read RDRF flag in SSR
Read TDRE flag in SSR
Read OER flag in SSR
All data received?
RDRF = 1
TDRE = 1
OER = 1
<End>
Yes
Yes
No
No
(Clocked Synchronous Mode)
Error processing
Yes
[1]
[2]
[3]
[4]
[1] Read SSR and check that the TDRE
[2] Read SSR and check that the RDRF
[3] To continue serial transmission/
[4] If an overrun error occurs, read the
For overrun error processing, see
flag is set to 1, then write transmit
data to TDR.
TDRE flag is automatically cleared to
0.
flag is set to 1, then read the receive
data in RDR.
RDRF flag is automatically cleared to
0.
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR.
TDRE flag is automatically cleared to
0. When data is read from RDR, the
RDRF flag is automatically cleared to
0.
OER flag in SSR, and after
performing the appropriate error
processing, clear the OER flag to 0.
Transmission/reception cannot be
resumed if the OER flag is set to 1.
figure 13.13.
When data is written to TDR, the
When data is read from RDR, the
When data is written to TDR, the