MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 516

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Appendix A Electrical Characteristics
A.12
This section summarizes the electrical characteristics of the various startup scenarios for oscillator and
phase-locked loop (PLL).
A.12.1
Table A-11 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the clock and reset generator (CRG) block description chapter.
A.12.1.1
The release level V
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
A.12.1.2
The release level V
if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
A.12.1.3
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V
the PORF bit in the CRG flags register has not been set.
516
Conditions are shown in
Num
1
2
3
4
5
6
7
8
Reset, Oscillator, and PLL Electrical Characteristics
C
D
D
D
D
P
P
T
T
Startup
DD5
POR
LVR
SRAM Data Retention
POR release level
POR assert level
Reset input pulse width, minimum input time
Startup from Reset
Interrupt pulse width, IRQ edge-sensitive
mode
Wait recovery startup time
LVR release level
LVR assert level
is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
PORR
LVRR
Table A-4
and the assert level V
and the assert level V
CQOUT
CQOUT
unless otherwise noted
Rating
no valid oscillation is detected, the MCU will start using the internal self
no valid oscillation is detected, the MCU will start using the internal self
Table A-11. Startup Characteristics
MC9S12NE64 Data Sheet, Rev. 1.1
PORA
LVRA
are derived from the V
are derived from the V
uposc
uposc
.
.
Symbol
PW
V
V
PW
V
V
n
t
PORR
PORA
WRS
LVRR
LVRA
RST
RSTL
IRQ
Min
0.97
2.25
192
20
2
DD
DD
supply. They are also valid
supply. They are also valid
Typ
Freescale Semiconductor
Max
2.07
2.55
196
14
Unit
n
t
t
ns
osc
cyc
V
V
osc
V
V