MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 338

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 11 Ethernet Media Access Controller (EMACV1)
not performed. If the FPET bit is set, frames with Ethertype matching the value in the ETYPE register are
accepted. If the FEMW bit is set, frames with Emware Ethertype are accepted. If the FIPV6 bit is set,
frames with Internet protocol version 6 Ethertype are accepted. If the FARP bit is set, frames with address
resolution protocol Ethertype are accepted. If the FIPV4 bit is set, frames with Internet protocol Ethertype
are accepted. If the FIEEE bit is set, frames with valid IEEE 802.3 length Ethertype are accepted.
11.4.2.2.2
PAUSE MAC Control Type
If the EMAC is in full-duplex mode and the RFCE bit is set, the receiver detects incoming PAUSE frames.
After a PAUSE destination address has been detected, the type/length field is checked looking for a type
value of 0x8808. If the type/length field does not contain this value, the frame is rejected; otherwise, the
MAC control function reads the frame looking for MAC control operation codes carried in the data field.
For more information on the function of MAC control, see
Section 11.4.5.1, “MAC Flow
Control.”
11.4.3
Transmitter
The transmit data, which the user must write to the transmit buffer, consists of the destination address
followed by the source address, type/length field, and the data field. The EMAC transmitter automatically
appends the preamble, SFD, and FCS necessary for a transmit frame. It also automatically appends pad
data to extend the data length to the 46-byte minimum frame length.
After a frame has been written to the transmit buffer and the corresponding transmit end-of-frame pointer
has been initialized, the EMAC transmitter is ready to transmit on the network. When a START command
is executed by writing to the TCMD field, the EMAC transmit logic asserts MII_TXEN and starts
transmitting the preamble sequence, the start frame delimiter, and then the frame information from the
transmit buffer. The EMAC transmits bytes least significant nibble first.
In half-duplex operation, the EMAC transmitter defers transmission if the network is busy and data
transmission is started after the interframe gap interval. In full-duplex mode, the carrier sense is ignored,
and data transmission is started after the interframe gap interval. See
Section 11.4.3.1, “Interframe
Gap,”
and
Section 11.4.3.2,
“Deferring.”
If a collision occurs within the collision window of 64 bytes during transmission of the frame (half-duplex
mode), the EMAC transmitter follows the specified backoff procedures and attempts to retransmit the
frame until the retry limit threshold is reached. See
Section 11.4.3.3, “Collision Detection and
Backoff.”
If the carrier sense is lost during transmission and no collision is detected in the frame, the EMAC sets the
CSLF status bit. The frame is transmitted normally and no retries are performed as a result of a CSLF error.
After the transmit frame is complete, the TXCIF bits are set. If not masked (TXCIE set to 1), the EMAC
generates the frame transmission complete interrupt.
11.4.3.1 Interframe Gap
When the network becomes idle, a network node waits for a brief period called the interframe gap (IFG),
and then transmits its frame. This is provided to allow a brief recovery time between frame reception for
the Ethernet interfaces. The minimum interframe gap time for back-to-back transmission is 96 bit times.
MC9S12NE64 Data Sheet, Rev. 1.1
338
Freescale Semiconductor