MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 126

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.4.7
Read:Anytime.
Write:Anytime.
This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port H.
PIEH[6:0] — Interrupt Enable Port H
3.3.2.4.8
Read:Anytime.
Write:Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSH register. To clear this flag, write a “1” to the corresponding bit in the PIFH register.
Writing a “0” has no effect.
PIFH[6:0] — Interrupt Flags Port H
126
1 = Interrupt is enabled.
0 = Interrupt is disabled (interrupt flag masked).
1 = Active edge on the associated bit has occurred (an interrupt will occur if the associated enable
0 = No active edge pending.
Module Base + $1E
Module Base + $1F
Reset:
Reset:
Read:
Read:
Write:
Write:
bit is set).
Writing a “1” clears the associated flag.
Writing a “0” has no effect.
Interrupt Enable Register (PIEH)
Interrupt Flag Register (PIFH)
Bit 7
Bit 7
—
—
0
0
= Reserved or unimplemented
= Reserved or unimplemented
Figure 3-29. Port H Interrupt Enable Register (PIEH)
PIEH6
PIFH6
Figure 3-30. Port H Interrupt Flag Register (PIFH)
6
0
6
0
MC9S12NE64 Data Sheet, Rev. 1.1
PIEH5
PIFH5
5
0
5
0
PIEH4
PIFH4
4
0
4
0
PIEH3
PIFH3
3
0
3
0
PIEH2
PIFH2
2
0
2
0
PIEH1
PIFH1
1
0
1
0
Freescale Semiconductor
PIEH0
PIFH0
Bit 0
Bit 0
0
0