MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 185
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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6.3
This section provides a detailed description of all memory and registers.
6.3.1
The memory map for the TIM16B4CV1 module is given below in
register is the address offset. The total address for each register is the sum of the base address for the
TIM16B4CV1 module and the address offset for each register.
Freescale Semiconductor
1
0x0024 – 0x002C Reserved
0x002E – 0x002F Reserved
0x0010 - 0x0017 Reserved
Address Offset
Memory Map and Register Definition
Always read 0x0000.
Module Memory Map
0x000A
0x000B
0x000C
0x000D
0x000E
0x001A
0x001B
0x001C
0x001D
0x001E
0x002D
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000F
0x0018
0x0019
0x001F
0x0020
0x0021
0x0022
0x0023
Timer Input Capture/Output Compare Select (TIOS)
Timer Compare Force Register (CFORC)
Output Compare 7 Mask Register (OC7M)
Output Compare 7 Data Register (OC7D)
Timer Count Register (TCNT(hi))
Timer Count Register (TCNT(lo))
Timer System Control Register1 (TSCR1)
Timer Toggle Overflow Register (TTOV)
Timer Control Register1 (TCTL1)
Reserved
Timer Control Register3 (TCTL3)
Reserved
Timer Interrupt Enable Register (TIE)
Timer System Control Register2 (TSCR2)
Main Timer Interrupt Flag1 (TFLG1)
Main Timer Interrupt Flag2 (TFLG2)
Timer Input Capture/Output Compare Register4 (TC4(hi))
Timer Input Capture/Output Compare Register 4 (TC4(lo))
Timer Input Capture/Output Compare Register 5 (TC5(hi))
Timer Input Capture/Output Compare Register 5 (TC5(lo))
Timer Input Capture/Output Compare Register 6 (TC6(hi))
Timer Input Capture/Output Compare Register 6 (TC6(lo))
Timer Input Capture/Output Compare Register 7 (TC7(hi))
Timer Input Capture/Output Compare Register 7 (TC7(lo))
16-Bit Pulse Accumulator Control Register (PACTL)
Pulse Accumulator Flag Register (PAFLG)
Pulse Accumulator Count Register (PACNT(hi))
Pulse Accumulator Count Register (PACNT(lo))
Timer Test Register (TIMTST)
Table 6-1. TIM16B4CV1 Memory Map
MC9S12NE64 Data Sheet, Rev. 1.1
Use
Table
6-1. The address listed for each
Memory Map and Register Definition
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
3
3
3
3
3
1
2
2
4
4
4
4
4
4
4
4
2
185
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