MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 482
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 18 Debug Module (DBGV1)
18.3.2.6
482
PORTK/XAB
PPAGE
Reset
Reset
Field
7
15:0
SEE NOTE 1
PAGSEL
W
W
R
R
NOTES:
1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00.
Bit 15
Bit 7
Comparator C Compare Bits — The comparator C compare bits control whether comparator C will compare
the address bus bits [15:0] to a logic 1 or logic 0. See
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Note: This register will be cleared automatically when the DBG module is armed in LOOP1 mode.
6
Debug Comparator C Register (DBGCC)
15
0
0
7
Figure 18-10. Comparator C Extended Comparison in BKP/DBG Mode
XAB21
PIX7
= Unimplemented or Reserved
= Unimplemented or Reserved
SEE NOTE 2
0
5
Figure 18-11. Debug Comparator C Register High (DBGCCH)
Figure 18-12. Debug Comparator C Register Low (DBGCCL)
Bit 14
Bit 6
14
0
0
6
XAB20
PIX6
0
4
Table 18-12. DBGCC Field Descriptions
XAB19
PIX5
Bit 13
Bit 5
MC9S12NE64 Data Sheet, Rev. 1.1
3
13
0
0
5
DBGCXX
EXTCMP
XAB18
PIX4
2
Bit 12
Bit 4
12
0
0
4
XAB17
PIX3
1
Description
Table
XAB16
BIT 0
PIX2
Bit 11
Bit 3
11
18-13.
0
0
3
Table
XAB15
BIT 15
PIX1
18-11.
Bit 10
Bit 2
10
0
0
2
XAB14
BIT 14
PIX0
DBGCXH[15:12]
BIT 13
Freescale Semiconductor
Bit 9
Bit 1
0
0
9
1
BIT 12
Bit 8
Bit 0
0
0
8
0
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